The present technology relates to a controller, an information processing system, a method of controlling a controller, and a program. More specifically, the present technology relates to a controller, an information processing system, a method of controlling a controller, and a program in which error correction by a soft-decision decoding algorithm is performed.
In recent years, information processing systems may use non-volatile memories (NVMs) or HDDs (Hard Disk Drives) as storages. In these storages, stored data may be corrupted, and may not be read correctly. Therefore, a typical information processing system generates an error detection and correction code (ECC), based on data that is to be stored, and stores the ECC in the storage. When the data is reproduced, the information processing systems is allowed to detect and correct an error in the data, based on the ECC.
When the error is corrected, based on the ECC, a soft-decision decoding algorithm may be used. The soft-decision decoding algorithm is an algorithm that corrects an error, based on a soft-decision value corresponding to probability that a bit in data is “1” or probability that the a bit in data is “0”. On the other hand, an algorithm that corrects an error, based on a hard-decision value indicating that a bit in data is “1” or “0” is referred to as a hard-decision decoding algorithm.
Although the soft-decision decoding algorithm has higher error correction capability than the hard-decision decoding algorithm, processing is complicated, thereby increasing a circuit size and processing time. Therefore, an apparatus in which a part of the soft-decision decoding algorithm is simplified to suppress increase in circuit size and the like has been proposed (for example, refer to Japanese Unexamined Patent Application Publication No. 2010-28408). More specifically, this apparatus uses a repeat mode soft-decision decoding algorithm in which a process of performing error correction by transmitting a soft-decision value generated in one of a variable node and a check node to the other one is repeated to simplify processing in the check node.